? semiconductor components industries, llc, 2000 november, 2000 rev.4 1 publication order number: mtb75n05hd/d mtb75n05hd preferred device power mosfet 75 amps, 50 volts nchannel d 2 pak this power mosfet is designed to withstand high energy in the avalanche and commutation modes. the energy efficient design also offers a draintosource diode with a fast recovery time. designed for low voltage, high speed switching applications in power supplies, converters and pwm motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. ? avalanche energy specified ? sourcetodrain diode recovery time comparable to a discrete fast recovery diode ? diode is characterized for use in bridge circuits ? i dss and v ds(on) specified at elevated temperature ? short heatsink tab manufactured not sheared ? specially designed leadframe for maximum power dissipation maximum ratings (t c = 25 c unless otherwise noted) rating symbol value unit draintosource voltage v dss 50 volts draintogate voltage (r gs = 1.0 m w ) v dgr 50 gatetosource voltage continuous v gs 20 drain current continuous drain current continuous @ 100 c drain current single pulse (t p 10 m s) i d i d i dm 75 65 225 amps total power dissipation derate above 25 c total power dissipation @ t a = 25 c (minimum footprint, fr4 board) p d 125 1.0 2.5 watts w/ c watts operating and storage temperature range t j , t stg 55 to 150 c single pulse draintosource avalanche energy starting t j = 25 c (v dd = 25 v, v gs = 10 v, peak i l = 75 a, l = 0.177 mh, r g = 25 w ) e as 500 mj thermal resistance junction to case junction to ambient junction to ambient (minimum foot- print, fr4 board) r q jc r q ja r q ja 1.0 62.5 50 c/w maximum temperature for soldering purposes, 1/8 from case for 10 seconds t l 260 c mtb75n05hd yww marking diagram & pin assignment marking diagram & pin assignment 1 gate 4 drain 2 drain 3 source 75 amperes 50 volts r ds(on) = 9.5 m w device package shipping ordering information mtb75n05hd d 2 pak 50 units/rail d 2 pak case 418b style 2 1 2 3 4 http://onsemi.com nchannel d s g mtb75n05hd = device code y = year ww = work week MTB75N05HDT4 d 2 pak 800/tape & reel preferred devices are recommended choices for future use and best overall value.
mtb75n05hd http://onsemi.com 2 electrical characteristics (t j = 25 c unless otherwise noted) characteristic symbol min typ max unit off characteristics draintosource breakdown voltage (c pk 2) (note 2.) (v gs = 0, i d = 250 m adc) temperature coefficient (positive) v (br)dss 50 54.9 vdc mv/ c zero gate voltage drain current (v ds = 50 v, v gs = 0) (v ds = 50 v, v gs = 0, t j = 125 c) i dss 10 100 m adc gatebody leakage current (v gs = 20 vdc, v ds = 0) i gss 100 nadc on characteristics (note 1.) gate threshold voltage (c pk 1.5) (note 2.) (v ds = v gs , i d = 250 m adc) threshold temperature coefficient (negative) v gs(th) 2.0 6.3 4.0 vdc mv/ c static draintosource onresistance (note 3.) (c pk 3.0) (note 2.) (v gs = 10 vdc, i d = 20 adc) r ds(on) 7.0 9.5 m w draintosource onvoltage (v gs = 10 vdc) (note 3.) (i d = 75 a) (i d = 20 adc, t j = 125 c) v ds(on) 0.63 0.34 vdc forward transconductance (v ds = 10 vdc, i d = 20 adc) g fs 15 mhos dynamic characteristics (note 2.) input capacitance (v ds =25v v gs =0 (c p k 20) c iss 2600 3900 pf output capacitance (v ds = 25 v , v gs = 0 , (c pk ? ? ? ?? ???? ?? ? 2.0) (c ) c oss 1000 1300 transfer capacitance )( k ) (c pk 2.0) c rss 230 300 switching characteristics (note 4.) turnon delay time t d(on) 15 30 ns rise time (v dd = 25 v, i d = 75 a, v gs =10v t r 170 340 turnoff delay time v gs = 10 v, r g = 9.1 w ) t d(off) 70 140 fall time r g 9.1 w ) t f 100 200 gate charge q t 71 100 nc (v ds = 40 v, i d = 75 a, q 1 13 (v ds 40 v , i d 75 a , v gs = 10 v) q 2 33 q 3 26 sourcedrain diode characteristics forward onvoltage (note 2.) (i s = 75 a, v gs = 0) (c pk 10) (i s = 20 a, v gs = 0) (is = 20 a, v gs = 0, t j = 125 c) v sd 0.97 0.80 0.68 1.00 vdc reverse recovery time t rr 57 ns (i s = 37.5 a, v gs = 0, t a 40 (i s 37 . 5 a , v gs 0 , di s /dt = 100 a/ m s) t b 17 reverse recovery stored charge q rr 0.17 m c internal package inductance internal drain inductance (measured from contact screw on tab to center of die) (measured from drain lead 0.25 from package to center of die) l d 3.5 4.5 nh internal source inductance (measured from the source lead 0.25 from package to source bond pad) l s 7.5 1. pulse test: pulse width 300 m s, duty cycle 2%. 2. reflects typical values. c pk = absolute value of (spec avg) / 3 * sigma). 3. for accurate measurements, good kelvin contact required. 4. switching characteristics are independent of operating junction temperature.
mtb75n05hd http://onsemi.com 3 typical electrical characteristics (note 5.) r ds(on) , drain-to-source resistance (ohms) r ds(on) , drain-to-source resistance (normalized) r ds(on) , drain-to-source resistance (ohms) i dss , leakage (na) 0 160 v ds , drain-to-source voltage (volts) figure 1. onregion characteristics i d , drain current (amps) v gs , gate-to-source voltage (volts) figure 2. transfer characteristics figure 3. onresistance versus drain current and temperature figure 4. onresistance versus drain current and gate voltage figure 5. onresistance variation with temperature figure 6. draintosource leakage current versus voltage 5 v t j = 25 c 100 60 20 0 12345 160 i d , drain current (amps) 120 80 40 20 0 0123 5 8 0.014 0.012 0.01 0.006 0.004 0 i d , drain current (amps) 20 t j = 100 c 25 c -55 c v gs = 10 v 0.009 0.008 0.005 0 i d , drain current (amps) 20 40 60 80 100 120 t j = 25 c 2 1.5 1 0.5 0 -50 t j , junction temperature ( c) -25 0 25 50 75 100 125 150 v gs = 10 v i d = 37.5 a 1000 100 0 v ds , drain-to-source voltage (volts) 015304050 25 c 100 c v gs = 10 v t j = -55 c 25 c 100 c 0.008 0.002 0.007 0.006 140 160 10000 10 40 80 120 140 1.5 2.5 3.5 4.5 0.5 140 100 60 6 47 40 60 80 100 120 140 510 2025 35 45 t j = 125 c 7 v 6 v 5. pulse tests: pulse width 250 m s, duty cycle 2%. v ds 10 v 15 v v gs = 10 v v gs = 0 v
mtb75n05hd http://onsemi.com 4 power mosfet switching switching behavior is most easily modeled and predicted by recognizing that the power mosfet is charge controlled. the lengths of various switching intervals ( d t) are determined by how fast the fet input capacitance can be charged by current from the generator. the published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. accordingly, gate charge data is used. in most cases, a satisfactory estimate of average input current (i g(av) ) can be made from a rudimentary analysis of the drive circuit so that t = q/i g(av) during the rise and fall time interval when switching a resistive load, v gs remains virtually constant at a level known as the plateau voltage, v sgp . therefore, rise and fall times may be approximated by the following: t r = q 2 x r g /(v gg v gsp ) t f = q 2 x r g /v gsp where v gg = the gate drive voltage, which varies from zero to v gg r g = the gate drive resistance and q 2 and v gsp are read from the gate charge curve. during the turnon and turnoff delay times, gate current is not constant. the simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in a rc network. the equations are: t d(on) = r g c iss in [v gg /(v gg v gsp )] t d(off) = r g c iss in (v gg /v gsp ) the capacitance (c iss ) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating t d(on) and is read at a voltage corresponding to the onstate when calculating t d(off) . at high switching speeds, parasitic circuit elements complicate the analysis. the inductance of the mosfet source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. the voltage is determined by ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. the mosfet output capacitance also complicates the mathematics. and finally, mosfets have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. the resistive switching time variation versus gate resistance (figure 9) shows how typical switching performance is affected by the parasitic circuit elements. if the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. the circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with boardmounted components. most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. power mosfets may be safely operated into an inductive load; however, snubbing reduces switching losses. gate-to-source or drain-to-source voltage (volts) c, capacitance (pf) figure 7. capacitance variation v gs v ds 8000 10 6000 2000 1000 4000 0 5 0 5 10152025 t j = 25 c v ds = 0 v gs = 0 7000 5000 3000 c iss c rss c iss c oss c rss
mtb75n05hd http://onsemi.com 5 figure 8. gatetosource and draintosource voltage versus total charge figure 9. resistive switching time variation versus gate resistance v gs , gate-to-source voltage (volts) 0 q g , total gate charge (nc) v ds , drain-to-source voltage (volts) 12 t, time (ns) 10 8 4 0 25 50 q 1 q 2 q 3 1000 100 10 1 r g , gate resistance (ohms) 1 10 100 t j = 25 c i d = 75 a 75 t j = 25 c i d = 75 a v dd = 35 v v gs = 10 v q t 60 50 40 30 20 10 0 v gs v ds 2 6 t d(off) t d(on) t r t f draintosource diode characteristics the switching characteristics of a mosfet body diode are very important in systems using it as a freewheeling or commutating diode. of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, emi and rfi. system switching losses are largely due to the nature of the body diode itself. the body diode is a minority carrier device, therefore it has a finite reverse recovery time, t rr , due to the storage of minority carrier charge, q rr , as shown in the typical reverse recovery wave form of figure 12. it is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. therefore, one would like a diode with short t rr and low q rr specifications to minimize these losses. the abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. the mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by high di/dts. the diode's negative di/dt during t a is directly controlled by the device clearing the stored charge. however, the positive di/dt during t b is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. therefore, when comparing diodes, the ratio of t b /t a serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. a ratio of 1 is considered ideal and values less than 0.5 are considered snappy. compared to on semiconductor standard cell density low voltage mosfets, high cell density mosfet diodes are faster (shorter t rr ), have less stored charge and a softer reverse recovery characteristic. the softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell mosfet diode without increasing the current ringing or the noise generated. in addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. 0.9 10 20 v sd , source-to-drain voltage (volts) figure 10. diode forward voltage versus current i s , source current (amps) 0 0.2 0.4 0.6 0.8 1 80 40 0 t j = 25 c v gs = 0 v 0.1 0.3 0.5 0.7 70 60 50 30 i s , source current (amps) t, time (ns) figure 11. reverse recovery time (t rr ) 40 -120 20 -20 -30 0 -40 -100 -60 -20 20 40 60 80 30 10 -10 -80 -40 0 di/dt = 300 a/ m s standard cell density high cell density t b t rr t a t rr
mtb75n05hd http://onsemi.com 6 safe operating area the forward biased safe operating area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. curves are based upon maximum peak junction temperature and a case temperature (t c ) of 25 c. peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in an569, atransient thermal resistance general data and its use.o switching between the offstate and the onstate may traverse any load line provided neither rated peak current (i dm ) nor rated voltage (v dss ) is exceeded, and that the transition time (t r , t f ) does not exceed 10 m s. in addition the total power averaged over a complete switching cycle must not exceed (t j(max) t c )/(r q jc ). a power mosfet designated efet can be safely used in switching circuits with unclamped inductive loads. for reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. the energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. although many efets can withstand the stress of draintosource avalanche at currents up to rated pulsed current (i dm ), the energy rating is specified at rated continuous current (i d ), in accordance with industry custom. the energy rating must be derated for temperature as shown in the accompanying graph (figure 12). maximum energy at currents below rated continuous i d can safely be assumed to equal the values indicated. 0 50 t j , starting junction temperature ( c) e as , single pulse drain-to-source figure 12. maximum rated forward biased safe operating area 0.1 1 100 v ds , drain-to-source voltage (volts) figure 13. maximum avalanche energy versus starting junction temperature 1 10 100 1000 avalanche energy (mj) i d , drain current (amps) r ds(on) limit thermal limit package limit 0.1 25 50 75 100 125 10 v gs = 20 v single pulse t c = 25 c 500 300 200 100 i d = 75 a 400 100 m s dc 175 150 450 350 250 150 1 ms 10 ms 10 m s t, time (s) figure 14. thermal response 0.1 1 0.01 1.0e-05 1.0e+01 r(t), effective transient thermal resistanc e (normalized) r q jc (t) = r(t) r q jc r q jc = 1.0 c/w max d curves apply for power pulse train shown read time at t 1 t j(pk) - t c = p (pk) r q jc (t) p (pk) t 1 t 2 duty cycle, d = t 1 /t 2 0.2 0.05 0.02 0.01 0.1 1.0e-04 1.0e-03 1.0e-02 1.0e-01 1.0e+00 d = 0.5 single pulse
mtb75n05hd http://onsemi.com 7 0 0.5 1 1.5 2.0 2.5 3 25 50 75 100 125 150 t a , ambient temperature ( c) p d , power dissipation (watts) figure 15. d 2 pak power derating curve r q ja = 50 c/w board material = 0.065 mil fr4 mounted on the minimum recommended footprint collector/drain pad size 450 mils x 350 mils package dimensions d 2 pak case 418b03 issue d style 2: pin 1. gate 2. drain 3. source 4. drain notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. seating plane s g d t m 0.13 (0.005) t 23 1 4 3 pl k j h v e c a dim min max min max millimeters inches a 0.340 0.380 8.64 9.65 b 0.380 0.405 9.65 10.29 c 0.160 0.190 4.06 4.83 d 0.020 0.035 0.51 0.89 e 0.045 0.055 1.14 1.40 g 0.100 bsc 2.54 bsc h 0.080 0.110 2.03 2.79 j 0.018 0.025 0.46 0.64 k 0.090 0.110 2.29 2.79 s 0.575 0.625 14.60 15.88 v 0.045 0.055 1.14 1.40 b m b
mtb75n05hd http://onsemi.com 8 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com tollfree from mexico: dial 018002882872 for access then dial 8662979322 asia/pacific : ldc for on semiconductor asia support phone : 3036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mtb75n05hd/d north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (monfri 2:30pm to 7:00pm cet) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (monfri 2:00pm to 7:00pm cet) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (monfri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, uk, ireland
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